Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. As semiconductor device size become smaller and smaller, it becomes critical to develop enhanced inspection and review devices and procedures.
One such inspection technology includes scanning electron microscopy. Images obtained via scanning electron microscopy commonly suffer from dynamic charging artifacts, such as streaking and non-uniformity. The presence of charging artifacts in a given image reduces the quality and accuracy of the image. Typically, dynamic charging artifacts are mitigated by adjusting imaging conditions, landing energy or extraction field. In addition, dynamic charging artifacts are reduced by imaging in “back scatter” mode, avoiding the measurement of secondary electrons, the source of the dynamic charging effects. However, prior approaches to mitigating dynamic charging require trial and error to identify the optimal conditions of the given sample. Further, the optimization of conditions, necessary to minimize dynamic charging, often comprise a variety of image quality characteristics, such as resolution and detail of top/bottom surfaces
As such, it would be advantageous to provide a system and method that provides reduced dynamic charging artifacts in scanning electron microscopy images so as to remedy the shortcomings of the conventional approaches identified above.